1. Technical Field
The present invention relates to a test apparatus and a test method for testing a memory under test, a computer program product to cause the test apparatus to function, and a recording medium. More particularly, the present invention relates to a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto.
2. Related Art
A known test apparatus designed to test a memory under test such as a semiconductor memory tests a plurality of memories under test concurrently. The test apparatus judges whether the individual addresses are acceptable in each memory under test, and stores thereon the judgment results of the individual addresses.
Referring to memories under test of a certain type, it is necessary to write unique data into each memory under test in accordance with the judgment results of the individual addresses. Such data is different among the memories under test that have been tested. This is the reason why the test apparatus has a plurality of memories in a one-to-one correspondence with the memories under test for storing the above-mentioned data for the corresponding memory under test. Each of the memories in the test apparatus stores data used to repair a defective address in the corresponding memory under test, data indicating manufacturing information, and the like.
Each of such memories in a conventional test apparatus has a memory that stores 1-bit data at each address thereof and an address pointer that sequentially designates the address in the memory. For example, when the test apparatus applies a pattern “101101” to one of the memories under test, the corresponding memory in the test apparatus stores the individual bit values of the pattern at different addresses. The corresponding memory in the test apparatus uses the address pointer to sequentially designate the respective addresses, to output the pattern.
Memories under test of a certain type are addressable for the repairing processing by the number of pulses of a signal supplied to a particular pin during the defective address repairing processing. Note that each memory under test has different addresses which should be subjected to the repairing processing. Therefore, the information indicating such addresses is stored on a corresponding one of the memories which are provided in the test apparatus in a one-to-one correspondence with the memories under test.
As mentioned above, the address signal is stored on the corresponding memory in the test apparatus. Here, note that the memories in the conventional test apparatus store 1-bit data at each address thereof. Therefore, the individual bit values of the address signal need to be stored on different addresses. For example, when the test apparatus performs the repairing processing on the address No. 32760 in one of the devices under test, the corresponding memory in the test apparatus is required to have at least 32760 addresses. This indicates that the test apparatus needs memories with a very large storage capacity.
Furthermore, the address signal indicating the address to be repaired needs to be generated based on the results of judging whether the individual addresses in each memory under test are acceptable and the generated address signal needs to be stored on the corresponding memory in the test apparatus. Here, the address signal needs to be stored on multiple addresses as mentioned above. Therefore, it takes a long time to store the address signal onto the corresponding memory in the test apparatus.
Therefore, it is an object of an aspect of the innovations herein to provide a test apparatus, a test method, a computer program product, and a recording medium, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.